Radio frequency (RF) power amplifiers are often used in wireless devices, such as cellular telephones. Extending the battery life is a key concern for users and manufacturers of these wireless devices. One of the key factors in determining the battery life of a wireless device is the power consumption of the RF power amplifiers. The RF power amplifiers are designed to operate into an optimal load impedance and are typically coupled to an antenna of the wireless device.
However, under a load mismatch condition, such as, for example, when the antenna of the wireless device approaches objects (e.g., metal structures, human contact, a hand, etc., in the near field of the antenna, or the like), the load impedance of the RF power amplifier changes and the RF power amplifier draws excess current. In some cases, the current can exceed more than two times the current drawn under an optimal load impedance. When the RF power amplifier draws excess current, the battery life of the wireless device is reduced. In addition, the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) linearity and distortion limits are often exceeded when the RF power amplifier draws excess current. This reduction in battery life and distortion limits of the wireless device is undesirable.
FIG. 1 illustrates a schematic diagram of a power-control circuit 100 according to the prior art. Power-control circuit 100 includes a low drop-out (LDO) circuit 102, RF amplifier stages A1-A3, a battery voltage VBATT, an RFIN signal, a RFOUT signal and a VRAMP signal. LDO circuit 102 includes a divider network R1 and R2, a comparator 104, and a transistor Q1. As the collector voltage VCC in the RF amplifier stages A1-A3 decreases, due to, for example, a load mismatch condition, comparator 104 senses voltage Vd across the divider network R1 and R2 and compares voltage Vd with VAMP. The output of comparator 104 is applied to transistor Q1, which adjusts collector voltage VCC until voltage Vd equalizes with the VRAMP signal, thereby substantially maintaining the collector voltage VCC at a specified voltage.
However, the use of power-control circuit 100 is disadvantageous, because LDO circuit 102 does not provide a mechanism to limit the amount of current that is driven into the RF amplifier stages A1-A3. For example, under a load mismatch condition, LDO circuit 102 will continue to drive as much current as is necessary in order to maintain the collector voltage VCC constant with respect to the VRAMP signal. Among other things, this reduces the efficiency of RF amplifier stages A1-A3 and decreases the battery life of the wireless device, which, as described above, is disadvantageous for users and manufacturers of these wireless devices.
Another disadvantage of power-control circuit 100 is that it adversely affects the characteristics of the power control loop of the LDO circuit, even under normal operation. For example, as the collector voltage VCC is ramping to a specified output limit, as defined by the VRAMP signal, a sharp discontinuity occurs when the collector voltage VCC equals the VRAMP signal. This sharp discontinuity is commonly referred to as a hard limit and causes various spurious emissions and unwanted harmonics in the frequency domain. These spurious emissions and unwanted harmonics are undesirable.